IBM’s 3D chip stacking process could revive a famous rule on computing power

IBM Research and Tokyo Electron (TEL) collaborated on a new breakthrough in 3D chipmaking that uses a novel method to keep Moore's Law in motion.

The two companies partnered on a chipmaking innovation that simplifies the process for producing wafers with 3D chip stacking technology, a press statement reveals.

They announced that they successfully implemented the new process for producing 300 mm silicon chip wafers for 3D chip stacking technology. It is the world's first 300 mm level example of this technology.

New chip-stacking process uses laser invisible to silicon

Chip stacking typically requires vertical connections between layers of silicon, called through-silicon vias (TSVs). The layers are usually extremely thin, having a thickness of less than 100 microns.

During the production process, each of these wafers is attached to a carrier wafer, which is usually made of glass that is temporarily bonded to the silicon. Once the wafer is processed, the glass carrier is then removed from the silicon with the use of ultraviolet lasers.

IBM and TEL's new process uses a 300 mm module with an infrared laser that carries out a debonding process. This process is transparent to silicon, meaning it allows standard silicon wafers to be used instead of glass wafers for the carrier. This means that silicon wafers can be bonded to other pieces of silicon, meaning glass carriers are no longer necessary in the manufacturing process.

IBM and TEL aim to alleviate the global chip shortage

The researchers behind the new method believe it can help to alleviate the strain on the global chip industry. "As the global chip shortage continues," IBM's statement reads, "We'll likely need novel ways to increase chip production capacity over the coming years. We hope our work will help cut down on the number of products needed in the semiconductor supply chain, while also helping drive processing power improvements for years to come."

IBM Research has been working with TEL since 2018 on this new process, which it says should also produce fewer defects and process issues during manufacturing that are associated with dissimilar wafer pairs. Next, the partners aim to further test their beta system to demonstrate how it can be implemented in the supply chain.

The global chip shortage came as a result of sky-high demand and factory disruptions caused by Covid. But even before the pandemic, the computer chip industry was feeling the pressure. Moore's Law, which states that the number of transistors on a microchip will double each year, was slowed down by the physical limitations of silicon. Experts say the transistor is approaching the point where it is as small as it can get while remaining functional, leading some to sound the death knell for Moore's Law. As a point of reference, IBM Research's smallest chip node is 2 nanometers wide.

Chip stacking is typically only used in high-end operations such as the production of high-bandwidth memory. However, it has the potential to expand the number of transistors in a specific volume. Moore's Law has traditionally focused on areas rather than volumes, meaning the new breakthrough allows the continuation of Moore's Law via a different interpretation of the famous 1965 observation. It may not be dead yet.